The ESP132 SBC design is based on the radiation hard LEON2 processor 32-bit SPARC V8 designed by Atmel (TSC697E). The LEON2 is the next generation of the ERC32 European 32-bit SPARC v7 processor.

ESP132 cPCI SBC

• LEON2 SPARC V8 high performance RISC architecture using the Atmel TSC697E single chip Processor implemented on a Rad Hard 0.18u CMOS process.
  • LEON2-FT 1.0.13 compliant
  • 8 Register windows
• Fault tolerant by design
  • Full Triple Modular Redundancy (TMR)
  • EDAC & parity protection
• Performance: 100 MIPS at 100 MHz
• On-chip Peripherals:
  • PCI Interface, 32-bit/33 MHz compliant with 2.2 PCI specification
  • EDAC and Parity Generator and Checker
  • Memory Interface with SDRAM controller, PROM and SRAM controllers
• SDRAM
  • 1024 Mbytes organized as 256 M X 32, with additional 16-bits ECC using Reed Solomon RS(12,8) 2^4 Galois field check-bits.
  • SDRAM based on 4 G-bit vertically stacked SDRAM modules from 3D-Plus using 512 M-bit SDRAM devices
• EEPROM
  • 8 M Bytes, parallel access EEPROM organized as 2 M X32 with EDAC functionality
  • Power Off mode
  • EEPROM based on 3D-Plus 1M x 8-bit modules (each module uses a stack of 8 Hitachi 128K X8-bit EEPROM dies.
• SU PROM
  • 128K Bytes minimum, 8-bit wide, Non-Volatile Rad-hard memory, high data retention & SEU immune.
• Radiation Hardness:
  • 80 KRad Si TID, no latchup.
  • SEL th > 60 Mev-cm2/mg (parts @ 70C)
  • SEU event rate < 1E-8 Error/da