The ESP032 Enhanced Space Processor Single Board Computer is designed for radiation Intensive Low Earth and Geo-synchronous Orbit, Interplanetary and Deep Space applications and is built to the highest mission critical and safety standards. A very high level of integration results in a low component count and high reliability.

ESP032 cPCI SBC

• Integer unit based on SPARC V7 RISC Architecture, 16 MIPS/4MFlops @ 20MHz
  • 32-bit address bus/ 32-bit data bus
  • 4 stage pipeline
• Powerful 32/64 bit Floating Point Unit implements the ANSI/IEEE-754 (1985) FP standard.
  • FP instructions executed concurrently with integer instructions
• 2 Mbytes of EEPROM (with Power-off mode)
• 64 Kbytes of start up PROM (optional)
• 4 Mbytes of SRAM plus EDAC check bits
• 512 Kbytes of additional PCI local memory accessible through the CPCI bus at 32-MHz
• Programmable Interrupt controller: 18 inputs (8 from backplane for CPCI & other I/O cards)
• Enhanced system Watch Dog Timer (WDT)
• DMA Controller with PCI Memory Access Arbiter
• Two General Purpose 32-bit Timers (GPT) and one Real-Time Clock Timer (RTCT)
• 16-bit General Purpose I/O's (GPIO) with registers programmable interrupt capability
• A high performance rad tolerant configurable FPGA provides a selection of the following interfaces:
  • CAN busses (dual redundant serial CAN buses, backplane and external I/F)
  • Master/Target PCI core with fully compliant 32-bit cPCI bus
  • Dual redundant 1553B data bus: Bus Controller (BC), or Remote Terminal (RT)
  • IEEE 1355 Spacewire serial node
• I/O interface transceivers (A/B 1553 Transceiver, RS-422, RS-485, LVDS) to support above busses on front panel connectors.
• Dual UART debug ports
• Extensive Built In Test (BITE) circuitry
  • All data paths parity protected
  • Digital watchdog timer
  • EDAC on the memory bus
  • Memory access protection
• IEEE 1149.1 Test Access Port (TAP)